School of Electronics, Electrical Engineering and Computer Science

FPGA acceleration of image processing algorithms

Internships Summer 2017/18

Proposed Project Title:

  • FPGA acceleration of image processing algorithms

Principal Supervisor(s):
  • Prof. Roger Woods

Project Description:

Interest is dramatically increasing in the use of Field Programmable Gate Arrays (FPGAs) in processing data due to power consumption reasons. This is because with the advent of dark silicon, where users are not able to turn on all of the devices at the one time, the ability to create a more efficient architecture using FPGA technology becomes increasingly attractive.

The project builds upon a highly interesting research programme currently been undertaken in the Electronics and Computer Engineering cluster which is looking to build multicore structures on FPGA which can be programmed using a dataflow-based programming software environment. The objective here will be to implement an image processing environment on an advanced computer platform and will give the student exposure to state-of-the-art technology. The student will be ably assisted by two researchers who are working in the area.

  • Identify a suitable algorithm for implementation of the FPGA-based platform
  • Understand FPGA-based processor architecture
  • Code up algorithm using the dataflow-based platform
  • Explore and analyse numerous implementations
  • Write up work to contribute to formal publication

Academic Requirements:

The scheme is open to all EEECS Undergraduates (apart from students on the BIT degree pathway and students who are due to graduate this summer)

General Information:

Each internship will last between 6-8 weeks and will pay a weekly stipend of £200.

Accommodation and travel costs are not provided under this scheme.

Start date: 19 June 2017

Duration: 8 Weeks

Location: 8th floor Ashby Building

Further information available at:

Contact details:

Supervisor Name: Prof. Roger Woods

Queens University of Belfast
Electronics and Computer Engineering,
School of EEECS,
Ashby Building,
Stranmillis Road,

Tel: +44 (0)28 90974081