Energy-Quality Scalable Processors under Dynamically Varying Operating Conditions

  • Energy-Quality Scalable Processors under Dynamically Varying Operating Conditions

School of Electronics, Electrical Engineering and Computer Science
& ECIT Global Research Institute

Proposed Project Title:
Energy-Quality Scalable Processors under Dynamically Varying Operating Conditions

Principal Supervisor:   Dr. Georgios Karakonstantis


Project Description:

Currently, manufacturers go to great lengths to guardband the manufactured hardware against any potential functional failure induced by the highly unreliable and dynamically varying nanometer silicon. Existing measures may have accomplished to hide any inaccurate hardware behaviour from the software layers and maintain acceptable yield levels, but unfortunately the large energy, performance, and area overheads that they incur limit their viability. The incurred overheads have urged research community to look for alternative computing paradigms in which even inaccurate computation and approximate storage could be accepted and any quality loss could be traded off for energy gains. Although existing studies may have shown the benefits of such a paradigm in a variety of application domains there is still a need for the integration of schemes for providing minimum quality guarantees under various operating conditions.    

The primary aim of this project is to investigate schemes based on data mining and analysis for minimizing at low cost the impact on system operation of any potential online failure that may be induced randomly. The inherent error resilience and certain statistical characteristics of various applications will be exploited for achieving adequately-reliable and energy efficient operation, while limiting or even avoiding the penalties incurred by traditional approaches. The developed mechanisms will also consider the use of approximate arithmetic units and caches/memories, which may help to save energy but be the source of deterministic errors the impact of which will also be minimized. The developed schemes will be integrated on a RISC-V processor ported on a FPGA and evaluated with a variety of popular multimedia, data-mining and HPC applications. Overall, the proposed framework will allow the adaptation of any system to dynamically changing operating conditions and user requirements and is expected to be beneficial for a variety of application domains from embedded to high-performance systems. 

The PhD studentship will be based at the Data-Science and Scalable Computing Center (DSSC) of the Queen’s Global Research Institute of Electronics, Communications and Information Technology (ECIT). 

Contact details

Supervisor Name: Georgios Karakonstantis                                      Tel: +44 (0)28 9097 6550
QUB Address:       CSB, 18 Malone Road, BT9 5BN                            Email: