FPGA-based Sparse Graph Analytics

  • FPGA-based Sparse Graph Analytics

School of Electronics, Electrical Engineering and Computer Science
& ECIT Global Research Institute

Proposed Project Title: FPGA-based Sparse Graph Analytics

Principal Supervisor: Dr. J. McAllister                     Second Supervisor: Prof. N. Robertson

Project Description:

Graph analytics problems, such as network attacks, community detection, infrastructure monitoring or social media analysis are computationally demanding operations which currently can only be realised by large-scale cloud computing resources. However, in order to allow a system to react to events in a graph, such as attacks on a computer network, this needs to be realised close to the data source, i.e. within edge computing nodes, or embedded devices themselves. The energy constraints of these devices are currently inadequate given the computational load and memory requirements of the algorithms.

There are three key challenges in making this possible.

  1. Dramatically increasing the performance-per-Watt of the devices used to realise graph analytics problems.
  2. Effectively exploiting sparsity in the problems.

Devices which address the first challenge already exist – Field Programmable Gate Array (FPGA) being a leading example. However, architectures to support graph analytics in general, or more specifically the sparse matrix arithmetic on which they rely do not exist and are a critical enabling technology.

This project addresses this challenge. It will develop an FPGA-based streaming graph analytics processor which increases the performance-per-Watt of graph analytics operations on FPGA by at least an order-of-magnitude (factor 10). Key to this capability is the effective exploitation of sparse matrix arithmetic by developing custom FPGA architectures which are domain and problem-specific.

The specific objectives of the project are:

  • Develop an understanding of spare matrix arithmetic and its application to graph analytics.
  • Develop a graph analytics custom computing architecture for FPGA to efficiently realise the key sparse matrix arithmetic operations.
  • Use to proposed platform to realise key graph analytics algorithms.
  • Optimise the architecture and/or its use based on observed performance/power metrics.
  • Present your work in leading international journals and conferences in the area. 

Contact details

Supervisor Name: John McAllister                                                                                       Tel: +44 (0)28 9097 1743
QUB Address: Institute of Electronics, Communications and Information Technology (ECIT)     Email: jp.mcallister@qub.ac.uk